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The Morning AbstractGood morning — 347 papers dropped on arXiv overnight. 9 matched your interests. Here's what matters.
Real-Time Decoding Pushes Logical Qubits Past the 0.1% Threshold
A joint MIT-Harvard group ran surface code error correction on 48 physical qubits using a custom FPGA decoder — achieving a 0.09% logical error rate per round, the lowest published for any real-time system.
Quantinuum sets a new two-qubit gate fidelity record at 99.97% using barium-171 ions with pulsed Raman transitions.
IBM releases first benchmarks for the 1,121-qubit Heron chip: 0.3% median two-qubit gate error with mid-circuit measurement on all qubits.
New variational algorithm outperforms standard QAOA by 12% on Max-Cut while using 40% fewer two-qubit gates.
Microsoft-Delft team demonstrates topological qubits maintaining 15 μs coherence at 1.2K — up from sub-microsecond at similar temperatures.
Why the FPGA Decoder Changes the Error Correction Timeline
The error correction bottleneck has never been about whether codes work in theory — it's about whether you can decode syndromes fast enough for real-time feedback. Previous demonstrations of below-threshold error rates (Google's 2024 Willow result at 0.14%, Quantinuum's 2025 work at 0.11%) decoded syndromes after the computation finished. That's fine for benchmarking, but useless for real algorithms that need mid-circuit corrections.
The MIT-Harvard team built a custom decoder on Xilinx Ultrascale+ FPGAs using a parallelized minimum-weight perfect matching (MWPM) algorithm. The key innovation is decomposing the matching problem into independent subgraphs that fit within the FPGA's on-chip SRAM, avoiding the memory bottleneck that killed previous real-time attempts. The result: 880 ns average decode latency on a distance-5 surface code, well within the ~10 μs window before qubit coherence degrades.
At 0.09% logical error per round, this is the lowest published rate for any real-time decoder — and the first to beat the ~0.1% threshold where adding more physical qubits actually suppresses errors exponentially rather than linearly. The team ran 10,000 consecutive correction rounds without the decoder falling behind, proving stability under sustained operation.
The catch: this was demonstrated on a distance-5 code (48 physical qubits → 1 logical qubit). Scaling to distance-11 or higher — where you get enough error suppression for useful algorithms — will require either larger FPGAs or a multi-chip decoder architecture. The team estimates a 4× increase in FPGA resources for distance-7, which is within reach of current hardware...